The present invention relates to an image decoding apparatus and can be used suitably, in particular, for an image decoding apparatus that receives bit streams coded using tiles in accordance with H.265 (HEVC: High Efficiency Video Coding).
As a next generation standard that follows H.264 (MPEG-4 AVC: Advanced Video Coding) which is a standardized image coding method, H.265/HEVC was approved by the International Telecommunication Union (ITU) and its standardization work is ongoing. In H.265/HEVC, coding with tiles is adopted as a type of coding tools. In H.265/HEVC, square pixel regions called CTBs (Coding Tree Blocks) which are units of coding and decoding are defined. In tile-based coding, a single image (one frame of image) is divided into a plurality of rectangular regions (these regions are called tiles or “blocks”), each of which is made up of a plurality of CTBs, coding is then performed independently for each region (tile), and coded results are combined into a single bit stream which is then output. At a decoding side to which a bit stream is input, reversely, decoding is performed for each region (tile) and decoded results are combined to restore one frame of image. Filtering is performed on data around the boundaries between tiles in order to prevent degradation in image quality, i.e., visible boundary lines.
Tile-based coding and decoding are appropriate for parallel processing. The reason for this is because it is possible to code image data independently for each tile and decode coded image data independently for each tile. In the case of multi-core software decoding with a plurality of parallel CPUs (Central Processing Units), parallel decoding can be performed with runs as many as the number of cores by assigning each tile to each CPU in executing tile decoding. In this process, all information obtained by tile decoding is stored into a memory. After decoding all tiles, filtering is performed on image data around the boundaries between tiles, using information stored in the memory; then, decoding of a single image (one frame of image) is completed.
A bit stream which has been coded by tile-based coding and transmitted needs to be always decoded by tile-based decoding. However, even if a transmitting end has a parallel hardware architecture fit for tile-based coding, a receiving end that performs decoding does not necessarily have similar parallel hardware architecture. Besides, a decoding apparatus that cannot identify what coding algorithm is applied by a coding apparatus needs to be configured such that it is capable of decoding bit streams coded by any coding algorithm. For instance, a decoding apparatus needs to be configured such that it is capable of decoding bit streams coded using tile-based coding as well as bit streams coded without using tile-based coding. In a case where a decoding apparatus employs multi-cores, such problems would arise that control becomes complicated to absorb a difference in degree of parallelism with respect to the coding side; and that, in an extreme case, one of the multiple CPUs can only be assigned to run effectively for decoding a bit stream for one frame coded with one tile. Hence, in most cases, a decoding apparatus has single-core or single-threaded hardware not parallelized and is configured to execute decoding of a plurality of tiles serially on a per-tile basis.
Patent Documents 1 and 2 disclose an image coding apparatus and method and an image decoding apparatus and method, which are based on the H.265/HEVC standard. A technique described in Patent Document 1 optimizes a quantization matrix in a case where there is a plurality of orders of scanning quantization coefficients within a block (tile). A technique described in Patent Document 2 optimizes a quantization matrix even if blocks (tiles) have a non-square shape. In each case, coding and decoding are performed for each of blocks (tiles) into which an image is divided by a block division unit.
Meanwhile, in the case of dividing a single image (one frame of image) into a plurality of regions such as tiles and coding and decoding the tiles, there is a problem in which tile boundary lines are made visible as unnatural lines and perceived as degradation in image quality.
Patent Documents 3 and 4 disclose an image processing technique for alleviating the appearance of tile boundary lines. An image compression and expansion apparatus described in Patent Document 3, when processing a still image having a plurality of components, changes the positions of tile boundaries for each component, thereby making the boundary lines unnoticeable when combined in an overlaying manner. A moving image processing apparatus described in Patent Document 4 changes the positions of tile boundaries for each frame, thereby making the boundary lines unnoticeable when combined in an overlaying manner.